2nm and Beyond
![From [1]](/api/media/6cda630f-5725-5292-a022-0ba5fffa7fd3)
Something I often refers to.
2023 3nm. N3
2024. 3nm N3E ( Real 3nm for Volume and Long Term Production )
2025 2nm. GAAFET ( also known as NanoSheet or RibbonFET )
2027 1.4nm / 14A ( Angstrom )
2029 1nm / 10A. Forksheet
2030 ~ Expect some delays & 10A to only arrive in 2030
2032. 7A Forksheet
2034. 5A. CFET
2036. 3A. CFET
2038. 2A. CFET
2040. 1.4A.
2042. 1A
Surprisingly we have another 20 years to go. But now this goes back to my original thesis, [3], I have written something similar on Anandtech / SemiWiki in 2016 but I wont link to it. The question is; How are we going to afford it?
I originally predict 5nm / 3nm era will be the node that stops making sense for economically. That was at the time without AI, ChatGPT, HyperScaler not clearly established, and zero Trillion Dollar Market Cap company, but the thesis remains the same. At some point companies can no longer afford leading edge node. If 2nm were 24K per wafer, you could expect it to reach 30K with Forksheet in 2030. Design Cost for Leading Edge are expected to reach $3B. AI Assisted Design could lower that quite a bit, but we could still expect $1.5B. That is $50 per 100mm2 chip assuming 100% yield excluding testing and packaging. On an average life cycle of 200M unit, 80% yield packaging and testing it would cost between $70 - $80 per chip alone. Ignoring other cost like IP per chip, R&D, Marketing etc. For Qualcomm they will have to sell it at $250 to $300.
Somewhere between now and 2030, the unit economics will break down. And the only way to move forward will be a three year cadence.
[1] https://www.imec-int.com/en/articles/imec-puts-complementary-fet-cfet-logic-technology-roadmap